The present invention relates to a dynamic random access memory (DRAM) having a function of simultaneously writing identical data to two or more memory cells having different addresses.
The DRAM is used as a main memory in most of electronic devices such as computers. The DRAM used as a main memory is required to perform high-speed operations, that is, to increase a data rate at the time of data write/read, in order to execute various processes at high speed.
In particular, in electronic devices (e.g. work stations for image-processing, video cameras, etc.) designed principally for image processing, a great deal of image data needs to be processed at high speed and thus image-processing DRAMs with special functions are widely used. At present, a synchronous graphics RAM (SGRAM) and a video RAM (VRAM) are known as such image-processing DRAMS.
One of the special functions of the image-processing DRAM is to simultaneously write identical data to two or more memory cells having different addresses ("block-write function"). This function is added to the DRAM on the basis of inherent properties of image data. Specifically, data units of pixels constituting one complete screen image (or "frame") are not necessarily different from one another at random. For example, when all or part of a frame has the same color, the data units of the pixels forming all or part of the frame may be the same. In such a case, the same data is written to memory cells of different addresses in image processing. If the block-write function of the DRAM is utilized, the data rate of write data at the time of writing can be substantially increased, and the high-speed image processing or high-speed screen display can be effected.
FIG. 1 schematically shows a conventional DRAM having the block-write function.
A DRAM 100 is used as a standard memory (general-purpose memory) or a memory within a DRAM-embedded LSI.
Each of memory array blocks 101 in the DRAM 100 includes a memory cell array and peripheral circuits necessary for data write/read, such as a row decoder, a column decoder and sense amplifiers. This example is based on the presupposition that each memory array block 101 has a function of simultaneously writing/reading 32-bit data. In this case, each memory array block 101 is connected to a multiplexer 102 over 32 DQ line pairs (data buses). In this example, since the DRAM 100 has four memory array blocks 101, the number of DQ line pairs (data buses) is 128.
A select signal and a mode signal are input to a decoder 103. For example, LSB (Lowest Significant Bit)-side two bits AC0 and AC1 of n-bit column address signals AC0, . . . , ACn-1 are assigned to the select signal. The decoder 103 decodes the 2-bit select signal and outputs a decode signal for selecting one of the four memory array blocks 101. Based on the decode signal, the multiplexer 102 connects the selected memory array block 101 to an I/O circuit (e.g. a buffer) 104.
In a normal-write mode, 32-bit data is input to the selected memory array block 101 via the I/O circuit 104 and the multiplexer 102. On the other hand, in a block-write mode, a mode signal is enabled. At this time, the decoder 103 outputs a decode signal for selecting two or more, e.g. all memory array blocks 101, irrespective of the value of the two-bit select signal. Thus, in the block-write mode, 32-bit data is input to two or more selected memory array blocks 101 via the I/O circuit 104 and multiplexer 102.
By virtue of the addition of the block-write function, the above-described DRAM can have a substantially higher data rate than the memory without the block-write function at the time of data write for image processing.
Besides, the data rate at the time of data write can also be enhanced by increasing the number of bits of data which can be simultaneously written to one memory array block 101. In this case, the number of DQ line pairs naturally increases in accordance with the increase in the number of bits of data which can be simultaneously written to one memory array block 101.
Recently, in order to increase the data rate, many memories have been developed wherein the number of bits of data which can be simultaneously written/read is increased. In particular, in a DRAM-embedded LSI (an LSI wherein a DRAM and logic elements are merged into one chip) in which a DRAM is embedded in a logic LSI, the number of I(input)/O(output) lines (hereinafter referred to as "I/O number"), i.e. the number of bits of data which can be simultaneously written/read, is very large (e.g. 128 bits).
If the block-write function is added to such a DRAM with a very high I/O number, the number of DQ line pairs (data buses) in the DRAM (the I/O number.times.the number of blocks) becomes very large. For example, if one I/O line is added, the number of DQ line pairs (data buses) in the DRAM increases by 1.times.N (N=the number of blocks). Accordingly, in the DRAM having the block-write function, the area occupied by the DQ line pairs increases considerably and the chip area increases.
As has been described above, the conventional DRAM, in particular, the DRAM for image processing which has the block-write function, has the disadvantage that the chip area considerably increases due to the increase in the I/O number.